By Laung-Terng Wang,Charles E. Stroud,Nur A. Touba

sleek electronics checking out has a legacy of greater than forty years. The creation of latest applied sciences, in particular nanometer applied sciences with 90nm or smaller geometry, has allowed the semiconductor to maintain speed with the elevated performance-capacity calls for from shoppers. accordingly, semiconductor try out expenditures were transforming into progressively and usually volume to forty% of trendy total product price.

This ebook is a finished advisor to new VLSI checking out and Design-for-Testability ideas that may permit scholars, researchers, DFT practitioners, and VLSI designers to grasp quick System-on-Chip try out architectures, for try debug and analysis of electronic, reminiscence, and analog/mixed-signal designs.

  • Emphasizes VLSI try out ideas and layout for Testability architectures, with a variety of illustrations/examples.
  • Most updated assurance to be had, together with Fault Tolerance, Low-Power checking out, disorder and blunder Tolerance, Network-on-Chip (NOC) checking out, Software-Based Self-Testing, FPGA trying out, MEMS checking out, and System-In-Package (SIP) checking out, which aren't but on hand in any checking out book.
  • Covers the complete spectrum of VLSI trying out and DFT architectures, from electronic and analog, to reminiscence circuits, and fault analysis and self-repair from electronic to reminiscence circuits.
  • Discusses destiny nanotechnology try out tendencies and demanding situations dealing with the nanometer layout period; promising nanotechnology attempt innovations, together with Quantum-Dots, mobile Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
  • Practical difficulties on the finish of every bankruptcy for students.

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